BS62UV256

R0201-BS62UV256

Revision

2.6

Sep.

2006

7

WRITE CYCLE 2

(1,6)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive. The

data input setup and hold timing should be referenced to the second transition edge of the

signal that terminates the write.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to

the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

The parameter is guaranteed but not 100% tested.

(11)

(2)

(4,10)

WE

CE

(7)

(8)

(8,9)

ADDRESS

(5)