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R5105N Datasheet(PDF) 8 Page - RICOH electronics devices division |
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R5105N Datasheet(HTML) 8 Page - RICOH electronics devices division |
8 / 14 page R5105N 8 OPERATION M When the power supply, VIN pin voltage becomes more than the released voltage (+VDET), after the released delay time (or the power on reset time tpLH), the output of RESETB becomes “H” level. N When the SCK pulse is input, the watchdog timer is cleared, and TW pin mode changes from the discharge mode to the charge mode. When the TW pin voltage becomes higher than VREFH, the mode will change into the discharge mode, and next watchdog time count starts. O Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of TW pin, RESETB="L". P When the VIN pin becomes lower than the detector threshold voltage(-VDET), RESETB outputs "L". ∗ Watchdog Timeout period/Reset hold time The watchdog timeout period and reset hold time can be set with an external capacitor to TW pin. The next equations describe the relation between the watchdog timeout period and the external capacitor value, or the reset hold time and the external capacitor value. tWD(s) = 3.1*10 6 × C (F) tWR(s)=TWD/9 The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor. During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next reset hold time RESETB pin outputs "L". After starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse is input during the time period "TWDI", the clock pulse is ignored. TWDI[s]=TWD/10 Released Delay Time (Power-on Reset delay time) The released delay time can be set with an external capacitor connected to the CD pin. The next equation describes the relation between the capacitance value and the released delay time (tpLH). tpLH(s)=3.7 ×106× C(F) When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay time will be shorter than tpLH which is expected. Minimum Operating Voltage We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100k Ω in the case of the Nch open-drain output type. RESETB Output RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate voltage source. Clock Pulse Input Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period. |
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