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AL4CS231 Datasheet(PDF) 2 Page - AverLogic Technologies Inc |
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AL4CS231 Datasheet(HTML) 2 Page - AverLogic Technologies Inc |
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2 / 2 page  AVERLOGIC TECHNOLOGIES, INC. TEL : 1 408 361-0400 e-mail: sales@averlogic.com URL: www.averlogic.com April 5, 2002 (512, 1k ,2k, 4k, 8k) x9 Memory Array Input Buffer Output Buffer Write Control Logic Read Control Logic Flag Logic Write Pointer Read Pointer Offset Regissers Reset Logic Input data bus Output data bus /OE WCLK /WEN1 /LD /RS RCLK /REN1 /FF /EF /PAF /PAE AL4CS2x1 FIFO Block Diagram WEN2 /REN2 The 9bit input and output ports operate independently at a maximum speed of 133 MHz. The built-in address decoder and pointer managing circuits provide a straightforward bus interface to serially read/write memory that reduces inter-chip design efforts. The AL4CS2x1 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible memory management. The input data is synchronous with a free- running clock (WCLK), and input-enable pins (/WEN1, /WEN2). Data is written into the FIFO on every clock when enable pins are asserted. The output is synchronous with the other free-running clock (RCLK) and enables (/REN1, /REN2). An Output Enable pin (/OE) is provided at the read port for tri-state control of the output port. The FIFOs can output two fixed flags, Empty Flag( /EF) and Full Flag (/FF), and two programmable flags, Almost-Empty (/PAE) and Almost-Full (/PAF). The offsets of the /PAE and /PAF flags are loaded when Load pin (/LD) goes low. These chips are available as a 32-pin TQFP and PLCC Package. DISTRIBUTED BY: |
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