©2003 -Copyright by AverLogic Technologies, Corp.

1-F-PMK008-0001

AL5DAxxxx

3.3V, 5V Asynchronous Dual-Port SRAM

1k/2k/4K/8K/16K/32K x 8/9/16/18-bit

Features

! True dual port memory cells up to 256/288Kb

! Fully asynchronous dual-port SRAM aimed at communications market

! Max. access time: 30 ns

! Separate upper byte and lower byte control for multiplexed bus compatibility (only for 16/18 bit

devices)

! Supports byte write/read for 16/18 bit devices

! On-chip arbitration logic support 3 modes: Busy, Interrupt and Semaphore

-

Busy scheme circuit arbitrate between 2 ports

-

interrupt mechanism allow port to port communication

-

Full hardware support of semaphore to permit software handshaking between ports

! Versatile pin select for Master or Slave mode:

IH

V

S

M/

=

IL

V

S

M/

=

! Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one

device

! Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)

! 3.3v and 5v series low power respectively

! Compatible and functionally equivalent to IDT or Cypress

! Available in 52-PLCC, 68-PLCC, 84-PLCC, 64-TQFP/STQFP, 80-TQFP, 100-TQFP

Architecture

S

M/

L

CE

L

OE

L

UB

L

LB

R

CE

R

OE

R

UB

R

LB

7/8L

-

0L

IO

-15/17L

8/9L

IO

R

W

R/

)

,

( 2

1

R

BUSY

R

SEM

)

( 2

R

INT

L

W

R/

)

,

(

2

1

L

BUSY

L

SEM

)

( 2

L

INT

15/17R

-

8/9L

IO

7/8R

-

0R

IO

9R

-

0R

A

-14R

10R

A

9L

-

0L

A

14L

-

10L

A