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T48C862M-TNQ Datasheet(PDF) 7 Page - ATMEL Corporation |
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T48C862M-TNQ Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 107 page  7 T48C862-R8 4590B–4BMCU–02/03 Figure 4. Tolerances of Frequency Modulation Using C 4 =9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of C Stray1 =CStray2 = 1 pF ±10%, a parallel capacitance of the crystal of C 0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz results. CLK Output An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. Clock Pulse Take Over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on the PLL transmitter block with ENABLE = H, and after 4 ms to assume the clock signal of the transmission IC, so the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of Z Load,opt = (166 + j226) W at 868.3 MHz. There must be a low resistive path to V S to deliver the DC current. The delivered current pulse of the power amplifier is 7.7 mA and the maximum output power is delivered to a resistive load of 475 W if the 0.53 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: Z Load =475 W || j/(2 ´p ´f ´ 0.53 pF) = (166 + j226) W thus results for the maximum out- put power of 5.5 dBm. The load impedance is defined as the impedance seen from the PLL transmitter block’s ANT1, ANT2 into the matching network. Do not confuse this large signal load imped- ance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 475 W where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit shown in Figure 5. Note that the component values must be changed to compensate the individual board parasitics until the PLL transmitter block has the right load impedance Z Load,opt = (166 + j226) W at 868.3 MHz. Also the damping of the cable used to measure the output power must be calibrated. ~ V S XTAL C Stray1 C M L M R S C 0 C Stray2 C 4 C 5 Crystal equivalent circuit C Switch |
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