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TMS470PLF111PGET Datasheet(PDF) 5 Page - Texas Instruments |
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TMS470PLF111PGET Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 63 page  TMS470PLF111 16/32-BIT RISC FLASH MICROCONTROLLER SPNS113 – OCTOBER 2006 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 device characteristics The PLF111 device is a derivative of the F05 Platform Architecture. Table 1, Device Characteristics, identifies all the characteristics of the PLF111 device except the SYSTEM and CPU, which are generic. Table 1. Device Characteristics CHARACTERISTICS DEVICE DESCRIPTION TMS470PLF111 COMMENTS FOR PLF111 MEMORY For device memory mapping, please see page 13. INTERNAL MEMORY Pipeline/Non-Pipeline 1 Bank 128K-Byte Flash 1 Bank 32K-Byte Flash with ECC 8K-Byte SRAM CRC, 1-channel Flash is pipeline-capable PERIPHERALS For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 6, Interrupt Priority (VIM)). For the peripheral address ranges, see Table 3, Peripheral Memory and Table 4, Peripheral Select Map with Address Range. CLOCK FMZPLL Frequency-modulated zero-pin PLL has no external loop filter pins. GENERAL-PURPOSE I/Os 34 I/O Ports A, B, C and D each have eight (8) external pins with external interrupt capability. Port E has only two (2) external pins. ECP YES LIN 2 (2-pin) Also supports SCI mode of operation CAN (HECC and/or SCC) SCC SPI 1 Three chip select pins. C2SIb 1 I2C 1 HET with XOR Share 29 I/O The high-resolution (HR) SHARE feature allows even-numbered HR pins to share the next higher odd-numbered HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. HET RAM 64-Instruction Capacity MibADC 10-bit, 16-channel 64-word FIFO Both the logic and registers for a full 16-channel MibADC are present. CORE VOLTAGE 1.8 V I/O VOLTAGE 5 V PINS 144 PACKAGE PGE |
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