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HSDL-3220-001 Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED |
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HSDL-3220-001 Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED |
3 / 19 page 3 Bandwidth Selection Timing The transceiver is in default SIR/ MIR mode when powered on. User needs to apply the following programming sequence to both the SD and TXD inputs to enable the transceiver to operate at FIR mode. Setting the transceiver to SIR/MIR Mode (9.6 kbit/s to 1.152 Mbit/s) 1. Set SD/Mode input to logic HIGH 2. TXD input should remain at logic LOW 3. After waiting for t S ≥ 25 ns, set SD/Mode to logic LOW, the HIGH to LOW negative edge transition will determine the receiver bandwidth 4. Ensure that TXD input re- mains low for t H ≥ 100 ns, the receiver is now in SIR/MIR mode 5. SD input pulse width for mode selection should be > 50 ns. Setting the transceiver to FIR (4.0 Mbit/s) Mode 1. Set SD/Mode input to logic HIGH VIH 50% tS tH VIL 50% 50% TXD SD/MODE VIL VIH 50% tS tH VIL 50% 50% TXD SD/MODE VIH VIL Figure 3. Bandwidth selection timing at SIR/MIR mode. Figure 4. Bandwidth selection timing at FIR mode. Transceiver I/O Truth Table Inputs Outputs TXD Light Input to Receiver SD LED RXD Note High Don’t Care Low On Not Valid Low High Low Off Low 12,13 Low Low Low Off High Don’t Care Don’t Care High Off High Notes: 12. In-band IrDA signals and data rates ≤ 4.0 Mbit/s 13. RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and strength of the incident intensity. 2. After SD/Mode input remains HIGH at > 25 ns, set TXD input to logic HIGH, wait t S ≥ 25 ns (from 50% of TXD rising edge till 50% of SD falling edge) 3. Then set SD/Mode to logic LOW, the HIGH to LOW negative edge transition will determine the receiver band- width 4. After waiting for t H ≥ 100 ns, set the TXD input to logic LOW 5. SD input pulse width mode selection should be > 50 ns. |
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