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X25170G Datasheet(PDF) 5 Page - IC MICROSYSTEMS |
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X25170G Datasheet(HTML) 5 Page - IC MICROSYSTEMS |
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5 / 15 page  X25170 Characteristics subject to change without notice. 5 of 15 Figure 1. Read E2PROM Array Operation Sequence Figure 2. Read Status Register Operation Sequence 012 3456 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 65432 10 Data Out CS SCK SI SO MSB High Impedance Instruction 16 Bit Address 15 14 13 3 2 1 0 0123456789 10 11 12 13 14 76543210 Data Out CS SCK SI SO MSB High Impedance Instruction Write Sequence Prior to any attempt to write data into the X25170, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25170. After all eight bits of the instruction are trans- mitted, CS must then be taken HIGH. If the user con- tinues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25170. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. |
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