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FM25L512-DG Datasheet(HTML) 6 Page - Ramtron International Corporation

Part No. FM25L512-DG
Description  512Kb FRAM Serial 3V Memory
Download  13 Pages
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Maker  RAMTRON [Ramtron International Corporation]
Homepage  http://www.ramtron.com
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FM25L512-DG Datasheet(HTML) 6 Page - Ramtron International Corporation

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FM25L512
Rev. 1.2
Aug. 2007
Page 6 of 13
CS
SCK
SI
SO
Hi-Z
0
1
2
3
4
5
6
7
0
0
0
0
0
1
0
0
Figure 6. WRDI Bus Configuration
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25L512 will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25L512 are
multi-tiered. A WREN op-code must be issued prior
to writing the memory (WRITE) or Status Register
(WRSR). Protecting the Status Register can be
accomplished via software using the WPEN bit or
hardware using the /WP pin. Status Register write
operations are blocked when /WP is low and
WPEN=1. Memory write operations are protected by
the block protect (BP) bits in the Status Register. The
state of the /WP pin has no effect on memory writes.
As described above, writes to the Status Register are
performed using the WRSR command and subject to
the WPEN bit and /WP pin. The Status Register is
organized as follows.
Table 2. Status Register
Bit
7
6
5
4
3
2
1
0
Name
WPEN
1
0
0
BP1
BP0
WEL
0


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