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NPE405H-3BA200C Datasheet(PDF) 1 Page - Applied Micro Circuits Corporation

Part # NPE405H-3BA200C
Description  PowerNP NPe405H Embedded Processor
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Manufacturer  AMCC [Applied Micro Circuits Corporation]
Direct Link  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

NPE405H-3BA200C Datasheet(HTML) 1 Page - Applied Micro Circuits Corporation

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Part Number NPe405H
Revision 1.01 – April 18, 2007
AMCC Proprietary
DS2011
1
NPe405H
PowerNP NPe405H Embedded Processor
Data Sheet
FEATURES
•PowerNPtechnology using an AMCC Pow-
erPC® 405 32-bit RISC processor core operat-
ing up to 266 MHz
PC-133 synchronous DRAM (SDRAM) inter-
face
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
External bus for peripheral devices
- Flash and ROM interface
- Direct support for 8-, or 16-, or 32-bit SRAM
and external peripherals
- Up to 8 devices
- External mastering supported
DMA support for external peripherals, internal
UARTs and memory
- Scatter-gather chaining supported
- Four channels
PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
- Asynchronous PCI bus interface
- Internal PCI bus arbiter which can be dis-
abled for use with an external arbiter
Four 10/100 Ethernet MACs supporting up to
four external PHYs via MII, RMII, or SMII inter-
faces
HDLC interface with 32 channels through two
ports at up to 4.096 Mbps each or 8.192 Mbps
for a single port
HDLC interface with 8 channels through 8
ports at 2.048 Mbps maximum
Programmable interrupt controller
- Seven external and 49 internal
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority ordering
- Programmable critical interrupt vector
Programmable timers
Two serial ports (16550 compatible UART)
One IIC interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal processor local bus (PLB) runs at
SDRAM interface frequency
Supports PowerPC processor boot from PCI
memory
User accessible performance counters
DESCRIPTION
Designed specifically to address embedded applica-
tions, the NPe405H provides a high-performance, low-
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power manage-
m ent fe atu r es an d lo wer p o we r d i s s ip atio n
requirements.
This chip contains a high-performance RISC proces-
sor core, SDRAM controller, PCI bus bridge, Ethernet
EMACs, HDLC controllers, external bus controller for
ROM, Flash, and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general pur-
pose I/O.
Technology: CMOS SA-12E 0.25
µm
(0.18
µm L
eff)
Package: 35mm, 580-ball enhanced plastic ball grid
array (E-PBGA)
Power (typical): 2.3 W at 133 MHz, 2.9 W at 200 MHz,
3.4W at 266MHz


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