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PPC440SPE Datasheet(PDF) 1 Page - Applied Micro Circuits Corporation |
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PPC440SPE Datasheet(HTML) 1 Page - Applied Micro Circuits Corporation |
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1 / 80 page  Part Number 440SPe Revision 1.23 - Sept 21, 2006 AMCC Proprietary 1 PowerPC 440SPe Embedded Processor Preliminary Data Sheet Features •PowerPC® 440 processor core operating up to 667 MHz with 32KB I- and D-caches (with parity checking) • On-chip 256KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory • Selectable Processor vs Bus clock ratios (Refer to the Clocking chapter in the PPC440SPe Embedded Processor User’s Manual for details) • Support up to 16 GB (4 Chip Selects) of 64-bit/32- bit SDRAM with ECC DDR I 266-333-400 DDR II 400-533-667 • Three PCI-Express serial interfaces: one 8 lanes and two 4 lanes - 2.5Gb/s per lane Root and Endpoint support. Opaque bridge • One 64-bit DDR PCI-X interfaces up to 133 MHz (DDR 266) with support for conventional PCI • Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives • Optional:16 Programmable Galois Field polynomials including 14d and 11d • XOR Accelerator with DMA controller • I2O messaging with two DMA controllers • External Peripheral Bus (16-bit Data, 27-bit Address) for up to three devices; Bank0=16 MB, Bank1 and Bank2=128 MB each • One Ethernet 10/100/1000Mbps half- or full- duplex interface. Operational modes supported are MII and GMII. • Programmable Interrupt Controller supports interrupts from a variety of sources. • Programmable General Purpose Timers (GPT) • Three serial ports (16750 compatible UART) • Two IIC interfaces • General Purpose I/O (GPIO) interface available • JTAG interface for board level testing • Processor can boot from PCI memory Description Designed specifically to address high-end embedded applications for storage, the PowerPC 440SPe (PPC440SPe) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, a DDR1/DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three PCI- Express interfaces, one DDR PCI-X bus interface, a 1Gbps Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O. Technology: CMOS Cu-11, 0.13mm Package: 27mm, 675-ball, 1mm pitch, Flip Chip- Plastic Ball Grid Array (FC-PBGA) Power (estimated): Less than 14W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V |
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