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PPC405GPR-3DB266Z Datasheet(PDF) 7 Page - Applied Micro Circuits Corporation |
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PPC405GPR-3DB266Z Datasheet(HTML) 7 Page - Applied Micro Circuits Corporation |
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7 / 57 page  405GPr – Power PC 405GPr Embedded Processor AMCC 7 Revision 2.04 – September 7, 2007 Data Sheet Address Map Support The PPC405GPr incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GPr processor through the use of mtdcr and mfdcr instructions. System Memory Address Map 4GB System Memory Function Subfunction Start Address End Address Size General Use SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions. 0x00000000 0xE7FFFFFF 3712MB 0xE8010000 0xE87FFFFF 8MB 0xEC000000 0xEEBFFFFF 44MB 0xEEE00000 0xEF3FFFFF 6MB 0xEF500000 0xEF5FFFFF 1MB 0xF0000000 0xFFFFFFFF 256MB Boot-up Peripheral Bus Boot 1 0xFFE00000 0xFFFFFFFF 2MB PCI Boot 2 0xFFFE0000 0xFFFFFFFF 128KB PCI PCI I/O 0xE8000000 0xE800FFFF 64KB PCI I/O 0xE8800000 0xEBFFFFFF 56MB Configuration Registers 0xEEC00000 0xEEC00007 8B Interrupt Acknowledge and Special Cycle 0xEED00000 0xEED00003 4B Local Configuration Registers 0xEF400000 0xEF40003F 64B Internal Peripherals UART0 0xEF600300 0xEF600307 8B UART1 0xEF600400 0xEF600407 8B IIC0 0xEF600500 0xEF60051F 32B OPB Arbiter 0xEF600600 0xEF60063F 64B GPIO Controller Registers 0xEF600700 0xEF60077F 128B Ethernet Controller Registers 0xEF600800 0xEF6008FF 256B Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved. |
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