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PPC405GP-3KE200CZ Datasheet(PDF) 6 Page - Applied Micro Circuits Corporation |
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PPC405GP-3KE200CZ Datasheet(HTML) 6 Page - Applied Micro Circuits Corporation |
6 / 59 page 405GP – Power PC 405GP Embedded Processor 6 AMCC Revision 2.03 – September 7, 2007 Data Sheet PPC405GP Embedded Controller Functional Block Diagram The PPC405GP is designed using the IBM® Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. PPC405 Processor Core DOCM IOCM DCU ICU OCM Control OCM SRAM DCR Bus 16KB On-chip Peripheral Bus (OPB) GPIO IIC UART UART MAL Ethernet DMA Bridge Processor Local Bus (PLB) SDRAM PCI Bridge Code Decompression External Bus Controller Controller Clock Control Reset Power Mgmt JTAG Trace Timers MMU MII Controller OPB Interrupt Controller Arb 32-bit addr 32-bit data 13-bit addr 32-bit data External Bus Master Controller Universal I-Cache D-Cache (4-Channel) (CodePack ™) 66 MHz max (async) DCRs 33 MHz max (sync) 8KB Arb |
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