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M13S128168A-6TG Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc.

Part # M13S128168A-6TG
Description  2M x 16 Bit x 4 Banks Double Data Rate SDRAM
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13S128168A-6TG Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128168A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
10/49
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
-
Apply VDD before or at the same time as VDDQ.
-
Apply VDDQ before or at the same time as VTT & VREF).
2. Start clock and maintain stable condition for a minimun of 200us.
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1
5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the
rest address pins, A1~A11 and BA1)
*1
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
*2
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
CLK
CL K
Co m m a n d
0
1
23
45678910
11
12
13
14
15
16
17
18
19
t RP
pr e c h a r g e
Al l Ban ks
EM R S
MR S
Dl l R e s e t
t RP
pr ech a r g e
Al l B a n k s
1s t A ut o
Re f r e s h
t RF C
2nd A ut o
Re f r e s h
t RF C
Mode
Regi ster Set
An y
C om m and
m i n . 20 0 C y c l e
P ower up & I ni t i al i z a t i on S eq uenc e


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