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M13S128324A-4BG Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc. |
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M13S128324A-4BG Datasheet(HTML) 7 Page - Elite Semiconductor Memory Technology Inc. |
7 / 49 page ESMT M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.8 7/49 AC Operating Test Conditions Parameter Value Unit Input reference voltage for clock (VREF) 0.5*VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 1.0 V/ns Input levels (VIH/VIL) VREF+0.35/VREF-0.35 V Input timing measurement reference level VREF V Output timing reference level VTT V AC Timing Parameter & Specifications (VDD = 2.375V~2.75V, VDDQ=2.375V~2.75V, TA =0 C ° to 70 C ° )(Note) (VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 0 C ° to 70 C ° (for speed -3.6)) -3.6 -4 -5 -6 Parameter Symbol Min Max Min Max Min Max Min Max CL2 7.5 12 7.5 12 7.5 12 7.5 12 CL2.5 6.0 12 6.0 12 6.0 12 6.0 12 CL3 5.0 12 5.0 12 5.0 12 6.0 12 Clock Period CL4 tCK 3.6 12 4.0 12 5.0 12 6.0 12 ns Access time from CLK/ CLK tAC -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Data strobe edge to clock edge tDQSCK -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns Clock to first rising edge of DQS delay tDQSS 0.8 1.2 0.8 1.2 0.8 1.2 0.8 1.2 tCK Data-in and DM setup time (to DQS) tDS 0.4 - 0.45 - 0.45 - 0.45 - ns Data-in and DM hold time (to DQS) tDH 0.4 - 0.45 - 0.45 - 0.45 - ns DQ and DM input pulse width (for each input) tDIPW 1.75 - 1.75 - 1.75 - 1.75 - ns Input setup time (fast slew rate) tIS 0.9 - 0.9 - 1.0 - 1.0 - ns Input hold time (fast slew rate) tIH 0.9 - 0.9 - 1.0 - 1.0 - ns Control and Address input pulse width tIPW 2.2 - 2.2 - 2.2 - 2.2 - ns DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS falling edge to CLK rising-setup time tDSS 0.2 - 0.2 - 0.2 - 0.2 - tCK DQS falling edge from CLK rising-hold time tDSH 0.2 - 0.2 - 0.2 - 0.2 - tCK Data strobe edge to output data edge tDQSQ - 0.4 - 0.4 - 0.45 - 0.45 ns Data-out high-impedance window from CLK/ CLK tHZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns Data-out low-impedance window from CLK/ CLK tLZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns * speed -4 (CL3) must set VDD/VDDQ = 2.7V ± 0.1V |
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