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ADP3808JCPZ-RL Datasheet(PDF) 11 Page - Analog Devices |
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ADP3808JCPZ-RL Datasheet(HTML) 11 Page - Analog Devices |
11 / 16 page ADP3808 Rev. 0 | Page 11 of 16 – + 3-/4-CELL SELECTION BOOTSTRAPPED SYNCHRONOUS DRIVER VIN CSP – + OSCILLATOR L1 VREF + VREG UVLO BIAS + CSM COMP CHARGE CURRENT SETPOINT BATTERY VOLTAGE ADJUST AGND CSADJ BAT EN + RT SW PGND VCC BST BATTERY 12.6V/16.8V 7.0V C10 0.1µF DRV SYSP SYSM ISYS LIMSET LOGIC CONTROL LIMIT SYSTEM DC/DC ADP3808 1/2 Q1 FD56990A C15 22µF C14 2.2µF 150kΩ R8 56Ω C8 0.22µF C11 C16 22µF C9 100nF 1/2 Q1 FD56990A 22µH RCS 20mΩ R4 510Ω R13 10Ω DRVREG CELLSEL DRVLSD IN EN VTH DRVLSD R2 510Ω – – + AMP2 – + – C13 22µF C1 2.2µF RSS 10mΩ AMP1 DRVL – + gm1 BAT 1V SYSP REFIN – + – + gm2 – + R9 3.3V R10 3.3V R11 3.3V R12 BATADJ EXTPWR Figure 16. Typical Application Circuit FINAL BATTERY VOLTAGE CONTROL As the battery approaches its final voltage, the ADP3808 switches from CC mode to CV mode. The change is achieved by the common output node of gm1 and gm2. Only one of the two outputs controls the voltage at the COMP pin. Both amplifiers can only pull down on COMP, such that when either amplifier has a positive differential input voltage, its output is not active. For example, when the battery voltage, VBAT, is low, gm2 does not control VCOMP. When the battery voltage reaches the desired final voltage, gm2 takes control of the loop, and the charge current is reduced. Amplifier gm2 compares the battery voltage to a programmable level set by pins BATADJ and REFIN. The target battery voltage is dependent on the state of the CELLSEL pin as CELLSEL sets the number of cells to be charged. Pulling CELLSEL high sets the ADP3808 to charge three cells. When CELLSEL is tied to ground, four cells are selected. CELLSEL has a 2 μA pull-up current as a fail-safe to select three cells when it is left open. The final battery voltage is programmable from 4.0 V to 4.5 V per cell. The programming voltage is applied to the BATADJ pin and is ratioed to the REFIN pin. The battery voltage VBAT is set according to Equation 2 and Equation 3. For CELLSEL > 2 V: REFIN BATADJ V BAT V 5 . 1 V 12 + = (2) For CELLSEL < 0.8 V: REFIN BATADJ V BAT V 2 V 16 + = (3) OSCILLATOR AND PWM The oscillator generates a triangle waveform between 1 V and 2 V, which is compared to the voltage at the COMP pin, setting the duty cycle of the driver stage. When VCOMP is below 1.0 V, the duty cycle is zero. Above 2.0 V, the duty cycle reaches its maximum. The oscillator frequency is set by the external resistor at the RT pin, ROSC, and is given by Equation 4. OSC OSC R f 9 10 41 × = (4) |
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