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HT46R51A Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT46R51A Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
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5 / 42 page  HT46R51A/HT46R52A Rev. 1.10 5 September 20, 2007 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of 4 system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch and decoding takes an instruction cy- cle while execution take the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruc- tion. Program Counter - PC For HT46R51A, the program counter (PC) is 10 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1024 addresses. For HT46R52A, the program counter (PC) is 11 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 2048 addresses. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external inter- rupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k O S C 2 ( R C o n l y ) P C Execution Flow Mode Program Counter *b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0 Initial Reset 00000000000 External Interrupt 00000000100 Timer/Event Counter Overflow 00000001000 A/D Converter Interrupt 00000001100 Skip Program Counter+2 Loading PCL PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *b10~*b0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits, PC10~PC8: Original PC counter, remain unchanged For the HT46R51A, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not ap- plicable. For the HT46R52A, since the program counter is 11 bits wide (b0~b10) |
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