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HT46R54A Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT46R54A Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 43 page  HT46R53A/HT46R54A Rev. 1.00 11 August 24, 2006 The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of the INTC), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a sub- routine call to location ²0CH² will occur. The related in- terrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the ²RETI² in- struction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an in- terrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter Overflow 2 08H A/D Converter Interrupt 3 0CH EMI, EEI, ETI, and EADI are used to control the en- abling/disabling of interrupts. These bits prevent the re- quested interrupt from being serviced. Once the interrupt request flags (TF, EIF, and ADF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. In- terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam- aged once the ²CALL² operates in the interrupt subrou- tine. Oscillator Configuration There are two oscillator circuits in the microcontroller. Both of them are designed for system clocks, namely the external RC oscillator and the external Crystal oscil- lator, which are determined by options. No matter what oscillator type is selected, the signal provides the sys- tem clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30k W to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC os- cillator provides the most cost effective solution. How- ever, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process varia- tions. It is therefore not suitable for timing sensitive op- erations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resona- tor can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillator can be disabled by options to conserve power). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the sys- tem enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65 ms at 5V. The WDT oscillator can be dis- abled by option to conserve power. Watchdog Timer - WDT The clock source of the WDT is implemented by a dedi- cated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This timer is designed to prevent a software mal-function or sequence jumping to an unknown location with unpre- dictable results. The watchdog timer can be disabled by an option. If the watchdog timer is disabled, all the exe- cutions related to the WDT result in no operation. The WDT clock (fS) is further divided by an internal counter to give longer watchdog time-outs. In the case of HT46R53A/Ht46R54A devices, the division ratio can be varied by selecting different configuration options to give 2 12 to 215 division ratio range. Once an internal WDT oscillator (RC oscillator with pe- riod of 65 ms normally) is selected, it is divided by 216 to get the time-out period of approximately 4.3s. This time-out period may vary with temperature, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation C r y s t a l O s c i l l a t o r R C O s c i l l a t o r O S C 2 O S C 1 O S C 1 O S C 2 f S Y S / 4 4 7 0 p F V D D System Oscillator |
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