HV633

3

Recommended Operating Conditions

Symbol

Parameter

Min

Typ

Max

Units

Conditions

f

SC

Shift clock operating frequency

12

MHz

f

DIN

Data-in frequency

24

MHz

t

SS

CSI/CSO pulse to shift clock setup time

40

ns

t

HS

CSI/CSO pulse to shift clock hold time

0

ns

t

WA

CSI pulse width

49

ns

t

DS

Data to shift clock setup time

20

ns

t

DH

Data to shift clock hold time

0

ns

t

WD

Data-in pulse width

24

ns

t

WLC

Load count pulse width

98

ns

t

DLCR

Load count to ramp delay

1.0

µs

t

DRCC

1

Ramp to count clock delay

0.47

µs

t

DSL

Shift clock to load count delay time

98

ns

t

CSC

Shift clock cycle time

98

ns

t

WSC

Shift clock pulse width

49

ns

t

CCC

Count clock cycle time

98

ns

t

WCC

Count clock pulse width

49

ns

Note 1: Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp V

ramp size time of 12µs for V

Logic Timing

Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

Conditions

t

CR

Cycle time of ramp signal

15

µs

t

RR

Ramp rise time

10.6

µs

t

HR

2

Ramp hold time

2

15

µs

t

FR

Ramp fall time

3

µs

C

V

Note 2: The maximum ramp hold time may be longer than 15 µs, but the output voltage HV

Symbol

Parameter

Min

Typ

Max

Units

V

DD

Low-voltage digital supply voltage

4.5

5.0

5.5

V

V

DD

Low-voltage analog supply voltage

4.5

5.0

5.5

V

V

IH

High-level input voltage (analog and digital)

V

V

DD

V

V

IL

Low-level input voltage (analog and digital)

0

1.0

V

-2.0

0

V

V

CTL

I

0

2.0

V

V

PP

High-voltage supply

-0.3

80

V

V

R

Ramp voltage

0

V

V

f

SC

Shift clock operating frequency (at V

12

MHz