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HV758DB1 Datasheet(PDF) 2 Page - Supertex, Inc

Part # HV758DB1
Description  HV758 짹90V 2.2A Ultrasound Pulser Demo Board
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Manufacturer  SUTEX [Supertex, Inc]
Direct Link  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV758DB1 Datasheet(HTML) 2 Page - Supertex, Inc

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HV758DB1
The PCB Layout Techniques
The large thermal pad at the bottom of the HV758 package
is connected to the V
SUB pins to ensure that it always has
the highest potential of the chip, in any condition. V
SUB is the
connection of the IC’s substrate. PCB designers need to
pay attention to the connecting traces as the output TXP1
to 4, TXN1 to 4 high-voltage and high-speed traces. In
particular, low capacitance to the ground plane and more
trace spacing need to be applied in this situation.
High-speed PCB trace design practices that are compatible
with about 50 - 100MHz operating speeds are used for the
demo board PCB layout. The internal circuitry of the HV758
can operate at quite a high frequency, with the primary speed
limitation being load capacitance. Because of this high speed
and the high transient currents that result when driving
capacitive loads, the supply voltage bypass capacitors and
the driver to the FET’s gate-coupling capacitors should be
as close to the pins as possible. The V
SS pin pads should
have low inductance feed-through connections that are
connected directly to a solid ground plane. The V
DD, VPP, VPF,
V
NF and VNN supplies can draw fast transient currents of up
to ±2.0A, so they should be provided with a low-impedance
bypass capacitor at the chip’s pins. A ceramic capacitor of
up to 0.22 - 1.0µF may be used. Minimize the trace length
to the ground plane, and insert a ferrite bead in the power
supply lead to the capacitor to prevent resonance in the
power supply lines. For applications that are sensitive to
jitter and noise and using multiple HV758 ICs, insert another
ferrite bead between V
DD and decouple each chip supply
separately.
To reduce inductance, pay particular attention to minimizing
trace lengths and using sufficient trace width. Surface
mount components are highly recommended. Since the
output impedance of HV758’s high voltage power stages is
very low, in some cases it may be desirable to add a small
value resistor in series with the output TXP1 to 4 and TXN1
to 4 to obtain better waveform integrity at the load terminals.
This will, of course, reduce the output voltage slew rate at
the terminals of a capacitive load. Be aware of the parasitic
coupling from the outputs to the input signal terminals of
HV758. This feedback may cause oscillations or spurious
waveform shapes on the edges of signal transitions. Since
the input operates with signals down to 1.2V, even small
coupling voltages may cause problems. Use of a solid
ground plane and good power and signal layout practices
will prevent this problem. Also ensure that the circulating
ground return current from a capacitive load cannot react
with common inductance to create noise voltages in the
input logic circuitry.
Testing the Integrated Pulser
The HV758 pulser demo board should be powered up with
multiple lab DC power supplies with current limiting functions.
The following power supply voltages and current limits have
been used in the testing: V
PP = 0 to +90V 5.0mA, VNN = 0
to -90V 5.0mA, V
DD = +10V 10mA, (VPP-VPF) = +10V 10mA,
(V
NF-VNN) = +10V 10mA. VCC = +3.3V 5.0mA for HV758 VLL,
not including the user’s logic circuits.
The power-up or down sequences of the voltage supply
ensure that the HV758 chip substrate V
SUB is always at the
highest potential of all the voltages supplied to the IC.
The (V
PP - VPF) and (VNF - VNN) are the two floating power
supplies. They are only 9.0V, but floating with V
PP and VNN.
The floating voltages can be trimmed within the range of
+8.0 to +12V to adjust the rising and falling time of the output
pulses for the best HD2. Do not exceed the maximum voltage
of +12V. The V
PP and VNN are the positive and negative high
voltages. They can be varied from 0 to +/-90V maximum.
Note when the V
PP = VNN = 0, the VPF and VNF in respect to
the ground voltage is -10V and +10V.
The on-board dummy load of 330pF//2.5kΩ should be
connected to the high voltage pulser output through the
solder jumper when using an oscilloscope’s high impedance
probe to meet the typical loading condition. To evaluate
different loading conditions, one may change the values of
RC within the current and power limit of the device.
In order to drive the user’s piezo transducers with a cable,
one should match the output load impendence properly to
avoid cable and transducer reflections. A 70 to 75Ω coaxial
cable is recommended. The coaxial cable end should be
soldered to the TX1 to 4 and GND directly with very short
leads. If a user’s load is being used, the on-board dummy
load should be disconnected by cutting the small shorting
copper trace in between the zero ohm resistors R7, R8, R9
or R10 pads. They are shorted by factory default.
All the on-board test points are designed to work with the
high impedance probe of the oscilloscope. Some probes
may have limited input voltage. When using the probe
on these high voltage test-points, make sure that V
PP/VNN
voltages do not exceed the probe limit. Using the high
impendence oscilloscope probe for the on-board test points,
it is important to have short ground leads to the circuit board
ground plane.
Precautions need to be applied to not overlap the logic-high
time periods of the control signals. Otherwise, permanent
damage to the device may occur when cross-conduction
or shoot-through currents exceed the device’s maximum
limits.


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