M58PR256LE datasheet(4/119 Pages) STMICROELECTRONICS

Part #	M58PR256LE

Description	256-Mbit, 512-Mbit or 1-Gbit (횞 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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4 / 119 page

Contents

M58PR256LE, M58PR512LE, M58PR001LE

4/119

5.3.1

Single word program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.2

Buffer program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.3

Buffer enhanced factory program method . . . . . . . . . . . . . . . . . . . . . . . 45

6

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.1

Control program mode status bit (SR9) . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2

Object program mode status bit (SR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3

Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 47

6.4

Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5

Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.6

Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.7

VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.8

Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.9

Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.10

Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 49

7

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1

Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2

X latency bits (CR14-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.3

Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.4

Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.5

Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8

Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.1

Deep power-down mode bit (ECR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2

Deep power-down polarity bit (ECR14) . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.3

Output driver control bits (ECR2-ECR0) . . . . . . . . . . . . . . . . . . . . . . . . . 56

9

Extended Flash array (EFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1

Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.2

Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3

Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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