11

HV9911

Note: The maximum current that can be sourced out of the

SC pin is limited to 100µA. This limits the minimum value

of the R

SLOPE

resistor to 25kΩ. If the equation for slope

compensation produces a value of R

SLOPE

less than this

value, then R

is recommended that R

- 50kΩ.

Current Sense

The current sense input of the HV9911 includes a built in

100ns (minimum) blanking time to prevent spurious turn off

due to the initial current spike when the FET turns on.

The HV9911 includes two high-speed comparators – one is

used during normal operation and the other is used to limit

the maximum input current during input under voltage or

overload conditions.

The IC includes an internal resistor divider network, which

steps down the voltage at the COMP pin by a factor of

15. This stepped-down voltage is given to one of the

comparators as the current reference. The reference to the

other comparator, which acts to limit the maximum inductor

current, is given externally.

It is recommended that the sense resistor R

as to provide about 250mV current sense signal.

Current Limit

Current limit has to be set by a resistor divider from the

1.25V reference available on the IC. Assuming a maximum

operating inductor current I

the voltage at the C

Note that this equation assumes a current limit at 120%

of the maximum input current. Also, if V

450mV, the saturation of the internal opamp will determine

the limit on the input current rather than the C

a case, the sense resistor R

reduces below 450mV.

It is recommended that no capacitor be connected between

C

chosen to be less than 1000pF.

FAULT Protection

The HV9911 has built-in output over-voltage protection

and output short circuit protection. Both protection features

are latched, which means that the power to the IC must

be recycled to reset the IC. The IC also includes a FAULT

pin which goes low during any fault condition. At startup, a

monoshot circuit, (triggered by the POR circuit), resets an

internal flip-flop which causes FAULT to go high, and remains

high during normal operation. This also allows the gate drive

to function normally. This pin can be used to drive an external

disconnect switch (Q2 in the Typical Boost Application

Circuit on pg.1), which will disconnect the load during a

fault condition. This disconnect switch is very important in a

boost converter, as turning off the switching FET (Q

an output short circuit condition will not remove the fault (Q

1

is not in the path of the fault current). The disconnect switch

will help to disconnect the shorted load from the input.

Over Voltage Protection

Over voltage protection is achieved by connecting the output

voltage to the OVP pin through a resistive divider. The voltage

at the OVP pin is constantly compared to the internal 1.25V.

When the voltage at this pin exceeds 1.25V, the IC is turned

off and FAULT goes low.

Output Short Circuit Protection

The output short circuit condition is indicated by FAULT. At

startup, a monoshot circuit, (triggered by the POR circuit),

resets an internal flip-flop, which causes FAULT to go high,

and remains high during normal operation. This also allows

the gate drive to function normally.

The steady state current is reflected in the reference

voltage connected to the transconductance amplifier. The

instantaneous output current is sensed from the FDBK

terminal of the amplifier. The short circuit threshold current is

internally set to 200% of the steady state current.

During short circuit condition, when the current exceeds the

internally set threshold, the SR flip-flop is set and FAULT

goes low. At the same time, the gate driver of the power FET

is inhibited, providing a latching protection. The system can

be reset by cycling the input voltage to the IC.

Note: The short circuit FET should be connected before the

current sense resistor as reversing R

accuracy of the output current (due to the additional voltage

drop across Q

Synchronization

The SYNC pin is an input/output (I/O) port to a fault tolerant

peer-to-peer and/or master clock synchronization circuit.

For synchronization, the SYNC pins of multiple HV9911

based converters can be connected together, and may also

be connected to the open drain output of a master clock.

When connected in this manner, the oscillators will lock

to the device with the highest operating frequency. When

synchronizing multiple ICs, it is recommended that the same

• 0.9