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ADSP-BF561SKBZ5002 Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-BF561SKBZ5002 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 64 page  Rev. B | Page 4 of 64 | June 2007 ADSP-BF561 MEMORY ARCHITECTURE The ADSP-BF561 views memory as a single unified 4G byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierar- chical structure to provide a good cost/performance balance of some very fast, low latency memory as cache or SRAM very close to the processor, and larger, lower cost and performance memory systems farther away from the processor. The ADSP-BF561 memory map is shown in Figure 3. The L1 memory system in each core is the highest performance memory available to each Blackfin core. The L2 memory pro- vides additional capacity with lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of physical memory. The memory DMA controllers provide high bandwidth data movement capability. They can perform block transfers of code or data between the internal L1/L2 memories and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF561 has four blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory of each Blackfin core consisting of 16K bytes of four-way set-associative cache mem- ory and 16K bytes of SRAM. The cache memory may also be configured as an SRAM. This memory is accessed at full proces- sor speed. When configured as SRAM, each of the two 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The second on-chip memory block is the L1 data memory of each Blackfin core which consists of four banks of 16K bytes each. Two of the L1 data memory banks can be configured as one way of a two-way set-associative cache or as an SRAM. The other two banks are configured as SRAM. All banks are accessed at full processor speed. When configured as SRAM, each of the four 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The third memory block associated with each core is a 4K byte scratchpad SRAM which runs at the same speed as the L1 mem- ories, but is only accessible as data SRAM (it cannot be configured as cache memory and is not accessible via DMA). Figure 2. Blackfin Processor Core SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 8 88 8 40 40 A0 A1 BARREL SHIFTER DATA ARITHMETIC UNIT CONTROL UNIT R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L ASTAT 40 40 32 32 32 32 32 32 32 LD0 LD1 SD DAG0 DAG1 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 SP FP P5 P4 P3 P2 P1 P0 DA1 DA0 32 32 32 PREG RAB 32 |
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