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SC4215ASTRT Datasheet(PDF) 7 Page - Semtech Corporation |
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SC4215ASTRT Datasheet(HTML) 7 Page - Semtech Corporation |
7 / 9 page 7 2007 Semtech Corp. www.semtech.com SC4215A POWER MANAGEMENT Introduction The SC4215A is intended for applications where high cur- rent capability and very low dropout voltage are required. It provides a very simple, low cost solution that uses very little PCB real estate. Additional features include an en- able pin to allow for a very low power consumption standby mode, and a fully adjustable output. Component Selection Input capacitor: A large bulk capacitance ≥ 10µF/A (out- put load) should be closely placed to the input supply pin of the SC4215A to ensure that Vin does not sag below 1.4V. Also a minimum of 4.7µF ceramic capacitor is rec- ommended to be placed directly next to the Vin pin. This allows for the device being some distance from any bulk capacitance on the rail. Additionally, input droop due to load transients is reduced, improving load transient re- sponse. Additional capacitance may be added if required by the application. Output capacitor: a minimum bulk capacitance of ≥ 10µF/A (output load), along with a 0.1µF ceramic de- coupling capacitor is recommended. Increasing the bulk capacitance will improve the overall transient response. The use of multiple lower value ceramic capacitors in parallel to achieve the desired bulk capacitance will not cause stability issues. Although designed for use with ce- ramic output capacitors, the SC4215A is extremely tol- erant of output capacitor ESR values and thus will also work comfortably with tantalum output capacitors. Noise immunity: in very electrically noisy environments, it is recommended that 0.1µF ceramic capacitors be placed from IN to GND and OUT to GND as close to the device pins as possible. Internal voltage selection: By connecting the FB pin to GND, an internal resistor divider will regulate the output voltage to 1.2V. If the FB pin is connected directly to the VO pin, the out- put voltage will be regulated to the 0.5V internal refer- ence. External voltage selection resistors: the use of 1% resistors, and designing for a current flow ≥ 10µA is recommended to ensure a well regulated output (thus R2 ≤ 50kΩ). Applications Information Enable: Pulling this pin below 0.4V turns the regulator off, reducing the quiescent current to a fraction of its operating value. A pull up resistor up to 400kOhms should be connected from this pin to the VIN pin in application where supply voltages of Vin < 1.9V is required. For ap- plications with higher voltages than 1.9V, EN pin could be left open or connected to VIN. Thermal Considerations The power dissipation in the SC4215A is approximately equal to the product of the output current and the input to output voltage differential: () O D I VOUT VIN P • − ≈ The absolute worst-case dissipation is given by: () Q(MAX) (MAX) O(MAX) (MIN) (MAX) D(MAX) I VIN I VOUT VIN P • + • − = For a typical scenario, V IN = 3.3V ± 5%, VOUT = 2.8V and I O = 1A, therefore: V IN(MAX) = 3.465V, VOUT(MIN) = 2.744V and IQ(MAX) = 1.75mA, Thus P D(MAX) = .722W. Using this figure, and assuming T A(MAX) = 70°C, we can cal- culate the maximum thermal impedance allowable to main- tain T J ≤ 150°C: () () C/W 110 .722 70 150 P T T R D(MAX) A(MAX) J(MAX) A)(MAX) TH(J ° = − = − = − This should be achievable for the SOIC-8EDP package us- ing PCB copper area to aid in conducting the heat away, such as one square inch of copper connected to the ground pins of the device. Internal ground/power planes and air flow will also assist in removing heat. For higher ambient temperatures it may be necessary to use additional cop- per area. |
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