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HT47C10-1 Datasheet(PDF) 6 Page - Holtek Semiconductor Inc |
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HT47C10-1 Datasheet(HTML) 6 Page - Holtek Semiconductor Inc |
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6 / 43 page  HT47R10A-1/HT47C10-1 Rev. 1.10 6 September 27, 2007 Functional Description Execution Flow The microcontroller system clock is derived from either a crystal or an RC oscillator. The system clock is inter- nally divided into four non-overlapping clocks. One in- struction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in the program memory are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction. A conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise it will proceed with the next instruction. The lower byte of the program counter (PCL) is a read- able and writeable register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Mode Program Counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial reset 0000000000 External interrupt 0000000100 Timer/event counter interrupt 0000001000 RTC interrupt 0000001100 Skip Program Counter+2 Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits S9~S0: Stack register bits @7~@0: PCL bits T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k I n s t r u c t i o n C l o c k P C Execution Flow |
Similar Part No. - HT47C10-1 |
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Similar Description - HT47C10-1 |
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