SC4601IMSTRT datasheet(5/18 Pages) SEMTECH

Part #	SC4601IMSTRT

Description	Low Input, High Efficiency Synchronous, Step Down Controller

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Manufacturer	SEMTECH [Semtech Corporation]

Direct Link	http://www.semtech.com

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5

 2006 Semtech Corp.

www.semtech.com

SC4601

POWER MANAGEMENT

Ordering Information

Pin Descriptions

r

e

b

m

u

N

t

r

a

Pe

c

i

v

e

D

)

1

(

R

T

S

M

I

1

0

6

4

C

S

0

1

-

P

O

S

M

T

R

T

S

M

I

1

0

6

4

C

S

)

2

(

B

V

E

1

0

6

4

C

Sd

r

a

o

B

n

o

it

a

u

l

a

v

E

VCC: Positive supply rail for the IC. Bypass this pin to

GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci-

tor.

GND: All voltages are measured with respect to this pin.

All bypass and timing capacitors connected to GND should

have leads as short and direct as possible.

FS: An external resistor connected with FS pin sets the

clock frequency.

SYNC/SLEEP: The oscillator frequency of SC4601 is set

by FS when SYNC/SLEEP is pulled and held above 2V. Its

synchronous mode operation is activated as the SYNC/

SLEEP is driven by an external clock. The oscillator and

PWM are designed to provide practical operation to 700kHz

when synchronized with V

IN ≤ 3.6V.

Sleep mode is in-

voked if SYNC/SLEEP is pulled and held below 0.8V which

can be accomplished by an external gate or transistor.

The Sleepmode supply current is 10µA typical.

VSENSE: This pin is the inverting input of the voltage

amplifier and serves as the output voltage feedback point

for the Buck converter. It senses the output voltage through

an external divider.

COMP: This is the output of the voltage amplifier. The

voltage at this output is connected to the inverting input

of the PWM comparator. A lead-lag network around the

voltage amplifier compensates for the two pole LC filter

characteristic inherent to voltage mode control and is

required in order to optimize the dynamic performance

of the voltage mode control loop.

PHASE, ISET: PHASE input is connected to the junction

between the two external power MOSFET transistors. The

voltage drop across the upper P-channel device is moni-

tored by PHASE and ISET during PFET conduction and

forms the current limit comparator and logic that sets

the PWM latch and terminates the PFET output pulse

once excessive voltage drop across the PFET is detected.

The controller stops switching and goes through a soft

start sequence once the converter output voltage drops

below 68.75% its nominal voltage. This prevents excess

power dissipation in the PMOSFET during a short circuit.

The current limit threshold is set by the external resistor

between VCC and ISET. The internal 50µA current source

has a positive temperature coefficient that can compen-

sate PMOSFET Rdson variation due to its junction tem-

perature change.

PDRV, NDRV: The PWM circuitry provides complemen-

tary drive signals to the output stages. The Cross con-

duction of the external MOSFETs is prevented by moni-

toring the voltage on the P-channel and N-channel driver

pins in conjunction with a time delay optimized for FET

turn-off characteristics.

Notes:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

(2) Lead free product. This product is fully WEEE and

RoHS compliant.

(10 Pin MSOP)

Pin Configuration

Top View

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