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HT82K96E Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT82K96E Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 44 page  HT82K96E Rev. 2.00 10 October 11, 2007 The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by ex- ecuting the ²HALT² or ²CLR WDT² instruction or dur- ing a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter- rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the SP is decremented. If immedi- ate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of INTC) will be set. · The access of the corresponding USB FIFO from PC · The USB suspend signal from PC · The USB resume signal from PC · USB Reset signal When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca- tion 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When PC Host access the FIFO of the HT82K96E, the corresponding request bit of USR is set, and a USB in- terrupt is triggered. So user can easy to decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When HT82K96E receive a USB Suspend signal from Host PC, the suspend line (bit0 of USC) of the HT82K96E is set and a USB interrupt is also triggered. Also when HT82K96E receive a Resume signal from Host PC, the resume line (bit3 of USC) of HT82K96E is set and a USB interrupt is triggered. Whatever there are USB reset signal is detected, the USB interrupt is triggered. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (; bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be re- set and the EMI bit cleared to disable further interrupts. The internal timer/even counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (;bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Bit No. Label Function 0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled) 1 EUI Controls the USB interrupt (1= enabled; 0= disabled) 2 ET0I Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) 3 ET1I Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled) 4 USBF USB interrupt request flag (1= active; 0= inactive) 5 T0F Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) 6 T1F Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) 7 ¾ Unused bit, read as ²0² INTC (0BH) Register |
Similar Part No. - HT82K96E_07 |
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Similar Description - HT82K96E_07 |
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