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SC2442/H

POWER MANAGEMENT

Application Information

Undervoltage Lockout

The undervoltage lockout circuitry monitors the AVCC pin.

During undervoltage lockout all output drives are turned

off and both SS pins are discharged to ground. Typically,

for AVCC increasing, normal operation will not occur until

AVCC reaches 4.6V. For AVCC falling, undervoltage lock-

out will not occur until AVCC falls below 4.5V.

Voltage Regulator

Using an external PNP transistor as shown in the Typical

Applications Circuit, the SC2442/H provide a regulated

AVCC supply. The same AVCC with adequate filtering can

be connected to PVCC to provide power for the output

drives. The AVCC is regulated at 7V typical which provides

optimum drive for most low Voltage power MOSFETs. The

BDI pin will provide at least 3 mA to regulate the external

PNP.

For VIN voltages below 8V, the PNP pass transistor will

always be operating in saturation and it is recommended

to connect VIN directly to AVCC and PVCC so long as

maximum input voltage is below 8V. The BDI pin may be

left unconnected. Alternately if an additional supply <8V is

available in addition to VIN, it can be used for separately

powering both the VCCs.

Soft Start and Hiccup Mode

The SC2442/H controllers utilize asynchronous start up

to provide glitch free output rise times. During start up, the

SS1 and SS2 pins are held low and the gate drive signals

are also pulled low. Once AVCC reaches 4.6V and above,

the SS capacitors are charged by a 10 μA internal current

source. The error amplifier outputs are clamped by the re-

spective SSx voltages. As the SSx pin voltage goes above

the oscillator valley voltage of 1.5V, the high-side driver

will begin switching. The low-side driver will not begin

switching until the SSx voltage has reached 3.3V.

During normal operation, the SC2442/H will enter hiccup

mode if the SS pin voltage is above 3.3V and the FB pin

voltage is below 0.525V (70% of 0.750V). If this occurs

the GDxH and GDxL signals will go low and the SS pin will

begin to sink 2 μA. The 2 μA of sink current will slowly

discharge the SS capacitor until its voltage reaches 1V,

which will trigger the SS pin to begin sourcing 10 μA. The

convertor will operate in the asynchronous mode during

hiccup.

Sync and Enable

When the SYNC/EN pin is pulled below 1V, all output

drives are turned off and both SS pins are discharged to

ground. When the SYNC/EN pin is pulled high above

1.8V, normal operation occurs. When an external clock

signal is applied that is marginally higher in frequency to

that set by the ROSC resistor, the internal oscillator will

synchronize to this signal. The external signal should have

TTL compatible transition.

Operating Frequency

The operating frequency is set by a resistor from ROSC

pin to AGND. ROSC sets the clock frequency Fc that is

twice the operating frequency of each converter. The

clock frequency is given by

Fc =

33,000 / ROSC

Fc is in kHz and ROSC is in kOhm.

Current Limiting

The SC2442/H provide cycle-by-cycle current limiting by

sensing the current in the input line. A non inductive resistor

should be used for precise current sensing and limiting.

When the voltage drop across a sense resistor in the input

line exceeds 105 mV, the PWM pulse is latched off and is

not reset until the next clock cycle. Overcurrent condition

affects only the high side driver. An RC filter should be

placed across the sense resistor as shown in the Typical

Application Circuit to reduce noise due to turn-on spikes.

The filter capacitor should be connected between VIN and

respective OCx pins for proper filtering. Typically a ceramic

or similar low esr capacitor is placed between the current

sense resistor and the switching circuit. If this capacitor

value is large, it can significantly distort the current

feedback waveform aross the sense resistors. This should

be taken into account while designing the overcurrent

protection circuit.

Gate Drive Considerations

The SC2442/H provide high side gate drive with

bootstrapping as shown in the Typical Application Circuit.

A ceramic capacitor is recommended between each BSTx

pin to the corresponding Phase Node. Each gate drive can

source and sink a minimum of 0.5A current with 100 nS

dead time between transistions to prevent shoot throughs.