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TMX320DM6437BZDUA Datasheet(PDF) 2 Page - Texas Instruments |
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TMX320DM6437BZDUA Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 309 page  www.ti.com 1.2 Description TMS320DM6437 Digital Media Processor SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007 – Management Data I/O (MDIO) Module • One 64-Bit Watch Dog Timer • VLYNQ™ Interface (FPGA Interface) • Two UARTs (One with RTS and CTS Flow Control) • Three Pulse Width Modulator (PWM) Outputs • Master/Slave Inter-Integrated Circuit (I2C • On-Chip ROM Bootloader Bus™) • Individual Power-Savings Modes • Two Multichannel Buffered Serial Ports • Flexible PLL Clock Generators (McBSPs) • IEEE-1149.1 (JTAG™) – I2S and TDM Boundary-Scan-Compatible – AC97 Audio Codec Interface • Up to 111 General-Purpose I/O (GPIO) Pins – SPI (Multiplexed With Other Device Functions) – Standard Voice Codec Interface (AIC12) • Packages: – Telecom Interfaces – ST-Bus, H-100 – 361-Pin Pb-Free PBGA Package – 128 Channel Mode (ZWT Suffix), 0.8-mm Ball Pitch • Multichannel Audio Serial Port (McASP0) – 376-Pin Plastic BGA Package – Four Serializers and SPDIF (DIT) Mode (ZDU Suffix), 1.0-mm Ball Pitch • 16-Bit Host-Port Interface (HPI) • 0.09-µm/6-Level Cu Metal Process (CMOS) • High-End CAN Controller (HECC) • 3.3-V and 1.8-V I/O, 1.2-V Internal • 32-Bit 33-MHz, 3.3-V Peripheral Component (-600/500/400) Interconnect (PCI) Master/Slave Interface • 3.3-V and 1.8-V I/O, 1.05-V Internal (-400) Conforms to PCI Specification 2.3 • Applications: • 10/100 Mb/s Ethernet MAC (EMAC) – Digital Media – IEEE 802.3 Compliant – Networked Media Encode/Decode – Supports Media Independent Interface (MII) – Video Imaging The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). TMS320DM6437 Digital Media Processor 2 Submit Documentation Feedback |
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