SN54LVTH16952, SN74LVTH16952

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS697G – JULY 1997 – REVISED APRIL 2000

7

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

SN54LVTH16952

SN74LVTH16952

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

150

150

150

150

MHz

tw

Pulse duration

CLK high or low

3.3

3.3

3.3

3.3

ns

t

Setup time

A or B before CLK

2.6

3.3

1.7

2.5

ns

tsu

Setup time

CLKEN before CLK

2.2

2.8

2

2.8

ns

th

Hold time

A or B after CLK

1

1

0.8

0

ns

th

Hold time

CLKEN after CLK

1.4

1.5

0.4

0

ns

(unless otherwise noted) (see Figure 1)

SN54LVTH16952

SN74LVTH16952

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

TYP†

MAX

MIN

MAX

fmax

150

150

150

150

MHz

tPLH

CLKBA or

AorB

1.6

5.7

7.4

1.3

2.7

4

4.4

ns

tPHL

CLKBA or

CLKAB

A or B

1.7

6

7

1.3

2.7

4

4.4

ns

tPZH

OEBA or OEAB

AorB

0.9

5

7.3

1

2.3

4

4.9

ns

tPZL

OEBA or OEAB

A or B

1.1

5.2

5.9

1

2.4

4

4.9

ns

tPHZ

OEBA or OEAB

AorB

1.7

6.7

7.3

2.1

3.9

5.7

6.2

ns

tPLZ

OEBA or OEAB

A or B

1.1

5.8

6

2.1

3.5

5.1

5.3

ns

† All typical values are at VCC = 3.3 V, TA = 25°C.