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TLV2548MFKB Datasheet(PDF) 1 Page - Texas Instruments

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Part # TLV2548MFKB
Description  3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLV2548MFKB Datasheet(HTML) 1 Page - Texas Instruments

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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Maximum Throughput 200-KSPS
D Built-In Reference, Conversion Clock and
8
× FIFO
D Differential/Integral Nonlinearity Error:
±1.2 LSB at –55°C to 125°C
D Signal-to-Noise and Distortion Ratio:
65 dB, fi = 12-kHz at –55°C to 125°C
D Spurious Free Dynamic Range: 75 dB,
fi = 12- kHz
D SPI/DSP-Compatible Serial Interfaces With
SCLK up to 20-MHz
D Single Wide Range Supply 3 Vdc to
5.5 Vdc
D Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
D Hardware Controlled and Programmable
Sampling Period
D Low Operating Current (1-mA at 3.3-V,
2-mA at 5.5-V With External Ref, 1.7-mA at
3.3-V, 2.4-mA at 5.5-V With Internal Ref)
D Power Down: Software/Hardware
Power-Down Mode (1
µA Typ, Ext Ref),
Autopower-Down Mode (1
µA Typ, Ext Ref)
D Programmable Auto-Channel Sweep
D Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SDO
SDI
SCLK
EOC/(INT)
VCC
A0
A1
A2
A3
A4
CS
REFP
REFM
FS
PWDN
GND
CSTART
A7
A6
A5
TLV2548Q . . . DW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDO
SDI
SCLK
EOC/(INT)
VCC
A0
A1
A2
CS
REFP
REFM
FS
PWDN
GND
CSTART
A3
TLV2544Q ...D PACKAGE
(TOP VIEW)
(TOP VIEW)
19
20
1
32
17
18
16
15
14
13
12
11
9
10
5
4
6
7
8
REFM
FS
PWDN
GND
CSTART
EOC/(INT)
VCC
A0
A1
A2
TLV2548M . . . FK PACKAGE
(TOP VIEW)
description
The TLV2544Q, TLV2548Q, and TLV2548M are a family of high performance, 12-bit low power, 3.5
µs, CMOS
analog-to-digital converters (ADC) which operate from a single 3-V to 5.5-V power supply. These devices have
three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input
(SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host
microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the
start of a serial data frame.
Copyright
 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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