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AKD4122 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AKD4122 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
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10 / 54 page  ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 10 - SWITCHING CHARACTERISTICS (Ta=25 °C; AVDD, DVDD=3.0 ∼ 3.6V; C L=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 36.864 MHz ns ns LRCK for Input data (LRCK1, LRCK2) Frequency Duty Cycle fs Duty 8 48 50 96 52 kHz % LRCK for Output data (LRCK, LRCK2) Frequency (Note 10) Duty Cycle Slave Mode Master Mode fs Duty Duty 32 48 50 50 96 52 kHz % % S/PDIF Clock Recover Frequency fPLL 32 96 kHz Audio Interface Timing Input for PORT1 BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “ ↑” (Note 11) BICK1 “ ↑” to LRCK1 Edge (Note 11) SDTI Hold Time from BICK1 “ ↑” SDTI Setup Time to BICK1 “ ↑” tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns Input for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “ ↑” (Note 11) BICK2 “ ↑” to LRCK2 Edge (Note 11) SDTIO Hold Time from BICK2 “ ↑” SDTIO Setup Time to BICK2 “ ↑” tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns Output for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “ ↑” (Note 11) BICK2 “ ↑” to LRCK2 Edge (Note 11) LRCK2 to SDTIO (MSB) (Except I 2S mode) BICK2 “ ↓” to SDTIO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns Note 10. Min value is 8kHz at BYPASS mode. Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge. BICK2 rising edge must not occur at the same time as LRCK2 edge. |
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