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AK4340 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4340 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 23 page ASAHI KASEI [AK4340] MS0501-E-00 2006/04 - 10 - OPERATION OVERVIEW System Clock The AK4340 requires MCLK, BICK and LRCK external clocks. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2) After exiting reset (PDN pin = “ ↑”), the AK4340 is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 3), and the internal master clock becomes the appropriate frequency (Table 4), it is not necessary to set DFS0/1. In parallel control mode, the sampling speed can be set by only ACKS pin. The internal DFS0 and DFS1 bits are fixed to “0”. Therefore, when ACKS pin is “L”, the AK4340 operates in Normal Speed Mode. The AK4340 operates in Auto Setting Mode at ACKS pin = “H”. In parallel control mode, the AK4340 does not support 128fs and 192fs of Double Speed Mode. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4340 is in the normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4340 may draw excess current and may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4340 should be reset by PDN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4340 should be in the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK4340 is in the power-down mode until MCLK and LRCK are input. DFS1 DFS0 Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~48kHz Default 0 1 Double Speed Mode 60kHz~96kHz 1 0 Quad Speed Mode 120kHz~192kHz Table 1. Sampling Speed (Manual Setting Mode) LRCK (kHz) MCLK(MHz) BICK (MHz) DFS1 DFS0 Sampling Speed fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs 0 0 32.0 - - 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480 0 0 44.1 - - 11.2896 16.9344 22.5792 33.8688 - 2.8224 0 0 Normal 48.0 - - 12.2880 18.4320 24.5760 36.8640 - 3.0720 0 1 88.2 11.2896 16.9344 22.5792 33.8688 - - - 5.6448 0 1 Double 96.0 12.2880 18.4320 24.5760 36.8640 - - - 6.1440 1 0 176.4 22.5792 33.8688 - - - - - 11.2896 1 0 Quad 192.0 24.5760 36.8640 - - - - - 12.2880 Table 2. System Clock Example (Manual Setting Mode) |
Similar Part No. - AK4340_06 |
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Similar Description - AK4340_06 |
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