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AKD4628 Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AKD4628 Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
11 / 41 page ASAHI KASEI [AK4628A] MS0385-E-00 2005/02 - 11 - SWITCHING CHARACTERISTICS (Ta=25 °C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C L=20pF) Parameter Symbol min typ max Units Master Clock Timing 256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 MHz ns ns MHz ns ns MHz ns ns LRCK Timing Normal mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 32 64 120 45 48 96 192 55 kHz kHz kHz % TDM256 mode (TDM0= “1”, TDM1= “0”) LRCK frequency “H” time “L” time fsn tLRH tLRL 32 1/256fs 1/256fs 48 kHz ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) LRCK frequency “H” time “L” time fsn tLRH tLRL 64 1/128fs 1/128fs 96 kHz ns ns Audio Interface Timing Normal mode (TDM0= “0”, TDM1= “0”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 18) BICK “ ↑” to LRCK Edge (Note 18) LRCK to SDTO(MSB) BICK “ ↓” to SDTO SDTI1-4,DAUX Hold Time SDTI1-4,DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 81 32 32 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns ns TDM256 mode (TDM0= “1”, TDM1= “0”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 18) BICK “ ↑” to LRCK Edge (Note 18) BICK “ ↓” to SDTO SDTI1 Hold Time SDTI1 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 18) BICK “ ↑” to LRCK Edge (Note 18) BICK “ ↓” to SDTO SDTI1-2 Hold Time SDTI1-2 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns Notes: 18. BICK rising edge must not occur at the same time as LRCK edge. |
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