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SN74TVC3010PWRE4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN74TVC3010PWRE4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically, 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended. The opposite side of the reference transistor is used as the reference voltage (VREF) connection. The VREF input must be less than VDDREF – 1 V to bias the reference transistor into conduction. The reference transistor regulates the gate voltage (VGATE) of all the pass transistors. VGATE is determined by the characteristic gate-to-source voltage difference (VGS) because VGATE = VREF + VGS. The low-voltage side of the pass transistors has a high-level voltage limited to a maximum of VGATE – VGS, or VREF. 200 k Ω VDDREF = 3.3 V 150 Ω 150 Ω 150 Ω 150 Ω Open-Drain CPU Interface Motherboard Interface 3 A2 4 A3 5 A4 12 A11 1 VDPU TVC3010 GATE† 24 B1 (VBIAS)† 23 2 A1 (VREF)† † VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. B2 22 B3 21 B4 20 B11 13 Figure 3. Typical Application Circuit |
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