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AK5700VN Datasheet(PDF) 26 Page - Asahi Kasei Microsystems |
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AK5700VN Datasheet(HTML) 26 Page - Asahi Kasei Microsystems |
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26 / 61 page  ASAHI KASEI [AK5700] MS0569-E-01 2006/12 - 26 - EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK5700 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), EXLRCK (fs) and EXBCLK ( ≥32fs). The master clock (MCKI) should be synchronized with EXLRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 11). Mode FS3-2 bits FS1 bit FS0 bit MCKI Input Frequency Sampling Frequency Range 0 Don’t care 0 0 256fs 7.35kHz ∼ 48kHz 1 Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz 2 Don’t care 1 0 512fs 7.35kHz ∼ 26kHz 3 Don’t care 1 1 256fs 7.35kHz ∼ 48kHz Default Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation (PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADC bit = “0”). AK5700 DSP or μP MCKI EXBCLK EXLRCK SDTO BCLK LRCK SDTI MCKO 1fs ≥ 32fs MCLK 256fs, 512fs or 1024fs Figure 22. EXT Slave Mode |
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