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AK5701KN Datasheet(PDF) 52 Page - Asahi Kasei Microsystems |
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AK5701KN Datasheet(HTML) 52 Page - Asahi Kasei Microsystems |
52 / 64 page [AK5701] 3. PLL Slave Mode (MCKI pin) EXBCLK pin EXLRCK pin MCKO bit (Addr:16H, D2) PMPLL bit (Addr:11H, D0) (1) Power Supply PDN pin PMVCM bit (Addr:10H, D2) (2) (3) MCKI pin (5) (4) Input MCKO pin Output (6) (7) 40msec(max) (8) Input Example: Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz (1) Power Supply & PDN pin = “L” “H” (3)Addr:10H, Data:04H (2)Addr:11H, Data:10H Addr:14H, Data:23H Addr:15H, Data:2FH (4)Addr:16H, Data:04H Addr:11H, Data:11H MCKO output start EXBCLK and EXLRCK input start Figure 47. Clock Set Up Sequence (3) <Example> (1) After Power Up: PDN pin “L” “H” “L” time of 150ns or more is needed to reset the AK5701. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” “1” VCOM should first be powered up before the other block operates. (4) Enable MCKO output: MCKO bit = “1” (5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max) at MCKI=12MHz (Table 4). (6) The normal clock is output from MCKO after PLL is locked. (7) The invalid frequency is output from MCKO during this period. (8) EXBCLK and EXLRCK clocks should be synchronized with MCKO clock. MS0404-E-02 2007/08 - 52 - |
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