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AK5701KN Datasheet(PDF) 6 Page - Asahi Kasei Microsystems |
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AK5701KN Datasheet(HTML) 6 Page - Asahi Kasei Microsystems |
6 / 64 page [AK5701] ANALOG CHARACTERISTICS (Ta=25 °C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter Min Typ max Units MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs) MGAIN1-0 bits = “00” 40 60 80 k Ω Input Resistance MGAIN1-0 bits = “01” or “10” 20 30 40 k Ω MGAIN1-0 bits = “00” - 0 - dB MGAIN1-0 bits = “01” - +15 - dB Gain MGAIN1-0 bits = “10” - +30 - dB MIC Amplifier: LIN+, LIN −, RIN+, RIN− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Input Voltage (Note 7) MGAIN1-0 bits = “01” - - 0.37 Vpp MGAIN1-0 bits = “10” - - 0.066 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 8) 2.02 2.25 2.48 V Load Resistance 0.5 - - k Ω Load Capacitance - - 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins (Single-ended inputs) → ADC → IVOL, MGAIN=+15dB, IVOL=0dB, ALC=OFF Resolution - - 16 Bits MGAIN=+30dB - 0.057 - Vpp MGAIN=+15dB 0.27 0.32 0.37 Vpp Input Voltage (Note 9) MGAIN=0dB 1.53 1.80 2.07 Vpp 67 77 - dB S/(N+D) ( −0.5dBFS) (Note 10) 79 87 - dB D-Range ( −60dBFS, A-weighted) (Note 11) S/N (A-weighted) (Note 11) 79 87 - dB Interchannel Isolation (Note 12) 80 90 - dB MGAIN=+30dB - 0.2 - dB MGAIN=+15dB - 0.2 1.0 dB Interchannel Gain Mismatch MGAIN=0dB - 0.2 0.5 dB Power Supplies: Power Supply Current: AVDD+DVDD Power Up (PDN pin = “H”) (Note 13) - 8 12 mA Power Down (PDN pin = “L”) (Note 14) - 1 20 μA Note 7. The voltage difference between LIN+/RIN+ and LIN −/RIN− pins. AC coupling capacitor should be connected in series at each input pin. Full-differential input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of LIN+, LIN −, RIN+ and RIN− pins is proportional to AVDD voltage, respectively. Vin = |(L/RIN+) − (L/RIN−)| = 0.123 x AVDD (max)@MGAIN1-0 bits = “01”, 0.022 x AVDD (max)@MGAIN1-0 bits = “10”. When the signal larger than above value is input to LIN+, LIN −, RIN+ or RIN− pin, ADC does not operate normally. Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ). Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = “01” (+15dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB). Note 10. 80dB(typ)@MGAIN=0dB, 70dB(typ)@MGAIN=+30dB Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB Note 12. 100dB(typ)@MGAIN=0dB, 80dB(typ)@MGAIN=+30dB Note 13. PLL Master Mode (MCKI=12MHz), PMADL = PMADR = PMVCM = PMPLL = PMMP = M/S bits = “1” and MCKO bit = “0”. MPWR pin outputs 0mA. AVDD=6.4mA(typ), DVDD=1.6mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=5.7mA(typ), DVDD=1.3mA(typ). Bypass Mode (THR bit = “1”, PMADL = PMADR = M/S bits = “0”), fs=8kHz: AVDD=1 μA(typ), DVDD=150 μA(typ). Note 14. All digital input pins are fixed to DVDD or DVSS. MS0404-E-02 2007/08 - 6 - |
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