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AK5701KN Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK5701KN Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
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8 / 64 page  [AK5701] MS0404-E-02 2007/08 - 8 - SWITCHING CHARACTERISTICS (Ta=25 °C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Output Timing Frequency Except DSP Mode 1 fs 7.35 - 48 kHz DSP Mode 1 (Note 18) fsd 14.7 - 96 kHz DSP Mode: Pulse Width High tLRCKH - tBCK - ns Except DSP Mode: Duty Cycle Duty - 50 - % BCLK Output Timing Period BCKO1-0 bit = “01” tBCK - 1/(32fs) - ns BCKO1-0 bit = “10” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % EXLRCK Input Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK −60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % EXBCLK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns PLL Slave Mode (PLL Reference Clock = EXLRCK pin) EXLRCK Input Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK −60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % EXBCLK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns Note 18. Sampling frequency is 7.35kHz ∼ 48kHz. |
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