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AK5701KN Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AK5701KN Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
11 / 64 page [AK5701] Parameter Symbol min typ max Units Control Interface Timing (CSP pin = “L”) CCLK Period tCCK 142 - - ns CCLK Pulse Width Low tCCKL 56 - - ns Pulse Width High tCCKH 56 - - ns CDTI Setup Time tCDS 28 - - ns CDTI Hold Time tCDH 28 - - ns CSN “H” Time tCSW 150 - - ns tCSS 50 - - ns CSN Edge to CCLK “ ↑” (Note 22) tCSH 50 - - ns CCLK “ ↑” to CSN Edge (Note 22) Control Interface Timing (CSP pin = “H”) CCLK Period tCCK 142 - - ns CCLK Pulse Width Low tCCKL 56 - - ns Pulse Width High tCCKH 56 - - ns CDTI Setup Time tCDS 28 - - ns CDTI Hold Time tCDH 28 - - ns CSN “L” Time tCSW 150 - - ns tCSS 50 - - ns CSN Edge to CCLK “ ↑” (Note 22) tCSH 50 - - ns CCLK “ ↑” to CSN Edge (Note 22) Power-down & Reset Timing PDN Pulse Width (Note 23) tPD 150 - - ns Note 24) PMADL or PMADR “ ↑” to SDTO valid ( HPF1-0 bits = “00” tPDV - 3088 - 1/fs HPF1-0 bits = “01” tPDV - 1552 - 1/fs HPF1-0 bits = “10” tPDV - 784 - 1/fs Note 22. CCLK rising edge must not occur at the same time as CSN edge. Note 23. The AK5701 can be reset by the PDN pin = “L”. Note 24. This is the count of LRCK “ ↑” from the PMADL or PMADR bit = “1”. MS0404-E-02 2007/08 - 11 - |
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