T436432B-5S datasheet(8/72 Pages) TMT

Part #	T436432B-5S

Description	2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM

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Manufacturer	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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TE

CH

tm

T436432B

TM Technology Inc. reserves the right

P. 8

Publication Date: FEB. 2007

to change products or specifications without notice.

Revision: A

READ A

NOP

WRITE B

NOP

CLK

DQM

COMM AND

DQ's

T0

T1

T2

T3

T4T5

T6T7

T8

NOP

DOUT A0

DINB0

DINB1

DINB2

Must be Hi-Z before

the Write Command

: "H" or "L"

Read to Write Interval (Burst Length • 4, CAS# Latency = 3)

CLK

DQM

COMMAND

T0

T 1

T2

T3

T4T5

T6T7

T8

NOP

BANKA

ACTIVATE

DIN A0

DIN A1

DIN A2

DIN A3

1 Clk Interval

CAS# latency=2

tCK2, DQ's

READ A

WRITE A

: "H" or "L"

Read to Write Interval (Burst Length

≥≥≥≥ 4, CAS# Latency = 2)

CLK

DQM

COMMAND

T0

T 1

T2

T3

T4T5

T6T7

T8

NOP

READ A

NOP

WRITE B

NOP

DIN B0

DIN B1

DIN B2

DIN B3

CAS# latency=2

tCK2, DQ's

NOP

: "H" or "L"

Read to Write Interval (Burst Length

≥≥≥≥ 4, CAS# Latency = 2)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll

command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll

command is issued in different CAS# latency.

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T436432B-5S Datasheet(PDF) 8 Page - Taiwan Memory Technology

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