T436432B-6S datasheet(9/72 Pages) TMT

Part #	T436432B-6S

Description	2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM

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Manufacturer	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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TE

CH

tm

T436432B

TM Technology Inc. reserves the right

P. 9

Publication Date: FEB. 2007

to change products or specifications without notice.

Revision: A

CLK

COMMAND

CAS# latency=2

tCK2, DQ's

T0

T 1

T2

T3T4

T5T6

T7T8

READ A

NOP

Activate

NOP

Precharge

CAS# latency=3

tCK3, DQ's

DOUT A0

DOUT A1

DOUT A2

DOUT A3

DOUT A0

DOUT A1

DOUT A2

DOUT A3

ADDRESS

tRP

Bank,

Col A

Bank(s)

Bank,

Row

Read to Precharge (CAS# Latency = 2, 3)

5

Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after the read

operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.)

+ burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge

function is ignored.

6

Write command

(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active row in an

active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write

bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data

elements will be registered on each successive positive clock edge (refer to the following figure). The DQs

remain with high-impedance at the end of the burst unless another command is initiated. The burst length and

burst sequence are determined by the mode register, which is already programmed. A full-page burst will

continue until terminated (at the end of the page it will wrap to column 0 and continue).

CLK

COM M A ND

T0

T1

T2T3T4

T5

T6

T7

T8

DIN A3

NOP

WRITE A

NOP

DIN A0

DIN A1

DIN A2

DQ0 - DQ3

The first data element and the write

are registeredon the same clock edge.

Extra data is masked.

don't care

Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)

A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from

Write command can occur on any clock cycle following the previous Write command (refer to the following

figure).

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T436432B-6S Datasheet(PDF) 9 Page - Taiwan Memory Technology

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