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AKD4631-VN Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AKD4631-VN Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
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3 / 44 page  ASAHI KASEI [AKD4631-VN] <KM077302> 2005/12 - 3 - (1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default) a) Set up jumper pins of MCKI clock “MCKPD bit” in the AK4631-VN should be set to “0”. X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X’tal of 11.2896MHz (Default) is set on the AKD4631-VN. Set “No.8 of SW3” to “H”. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator. b) Set up jumper pins of BICK clock Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4631-VN. There is no necessity for set up JP19. c) Set up jumper pins of FCK clock d) Set up jumper pins of DATA When the AK4631VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following. JP17 XTE MCLK_SEL JP21 JP18 MKFS 256fs 512fs 1024fs XTL DIR EXT MCKO JP6 MCKI JP22 FCK_SEL 2fs EXT JP28 FCK ADC DIR 1fs JP26 4631_SDTI ADC DAC/LOOP JP30 SDTI DIR ADC JP29 JP20 BICK JP27 BICK_INV THR INV DIR ADC BICK THR INV BICK_SEL JP19 EXT 16fs 32fs 64fs |
Similar Part No. - AKD4631-VN |
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Similar Description - AKD4631-VN |
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