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GL9711 Datasheet(PDF) 9 Page - GENESYS LOGIC |
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GL9711 Datasheet(HTML) 9 Page - GENESYS LOGIC |
9 / 42 page GL9711 PCI Express TM PIPE x1 PHY ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 9 CHAPTER 2 FEATURES l Complies with PCI Express Base Specification rev. 1.0a l Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 l Integrates 2.5 gigabit per second (Gpbs) Serializer/Deserializer l Supports 8-bit or 10-bit parallel interface @250MHz l Supports 16-bit parallel interface @125MHz l Supports DDR configuration for 8-bit or 10-bit mode l Beacon transmission and reception l Receiver detection l Transmission and detection of electrical idle l Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link l On-chip 8-bit/10-bit encoding/decoding and comma alignment l On-chip PLL provides clock synthesis l 1.8-V power supply for core l 2.5-V power supply for IO l Above 2.0 kV ESD protection l 0.18 µm process l Available in LFBGA-233 package |
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Similar Description - GL9711 |
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