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Issue A

ML145053

LANSDALE Semiconductor, Inc.

Figure 9. Timing for 10-Clock Transfer Using CS

Figure 10. Timing for 10-Clock Transfer Not Using CS

NOTES:

1. D9, D8, D7, D6, D5, …, D0 = the result of the previous A/D conversion.

2. A3, A2, A1, A0 = the mux address for the next A/D conversion.

CS

Dout

D9–MSB

MSB

12

3

4

56789

10

1

D8

D7

D6

D5

D4

D3

D2

D1

D0

D9–MSB

MSB

12

3

4

56789

10

D8

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D9

A3

1

D9

A3

HIGH IMPEDANCE

LOW LEVEL

RE-INITIALIZE

A/D CONVERSION

INITERVAL

A/D CONVERSION

INITERVAL

SHIFT IN NEW MUX ADDRESS,

SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE

SHIFT IN NEW MUX ADDRESS,

SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE

Din

SCLK

EOC

INITIALIZE

CS

MUST BE HIGH ON POWER UP

Dout

Din

SCLK

EOC

INITIALIZE