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ADS8515IDB Datasheet(PDF) 10 Page - Texas Instruments

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Part # ADS8515IDB
Description  16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS8515IDB Datasheet(HTML) 10 Page - Texas Instruments

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READING DATA
PARALLEL OUTPUT (After a Conversion)
PARALLEL OUTPUT (During a Conversion)
ADS8515
SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007
The ADS8515 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table 2
for ideal output codes and Figure 20 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2's COMPLEMENT
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full-scale range
±10 V
Least significant bit (LSB)
305
µV
Full scale (10 V-1 LSB)
9.999695 V
0111 1111 1111 1111
7FFF
Midscale
0 V
0000 0000 0000 0000
0000
One LSB below midscale
-305
µV
1111 1111 1111 1111
FFFF
-Full scale
-10 V
1000 0000 0000 0000
8000
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n is available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch the
data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications.
After conversion n has been initiated, valid data from conversion –1 can be read and is valid up to t2 after the
start of conversion n. Do not attempt to read data from t2 after the start of conversion n until BUSY (pin 26) goes
high; this may result in reading invalid data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing
specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter's performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 21.
Table 3. Conversion Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tw1
Pulse duration, convert
40
ns
ta
Access time, data valid after R/C low
0.8
1.2
µs
tpd
Propagation delay time, BUSY from R/C low
6
20
ns
tw2
Pulse duration, BUSY low
2
µs
td1
Delay time, BUSY after end of conversion
5
ns
td2
Delay time, aperture
5
ns
tconv
Conversion time
2
µs
tacq
Acquisition time
2
µs
tdis
Disable time, bus
10
15
83
ns
td3
Delay time, BUSY after data valid
35
50
ns
tv
Valid time, previous data remains valid after R/C low
1.5
2
µs
tconv + tacq
Throughput time
4
µs
tsu
Setup time, R/C to CS
10
ns
tc
Cycle time between conversions
4
µs
ten
Enable time, bus
10
15
30
ns
td4
Delay time, BYTE
10
15
30
ns
10
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8515


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