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DEVICE INFORMATION

VDIG

VANA

BUSY

CS

R/C

BYTE

D0 (LSB)

D1

D2

D3

D4

D5

D6

D7

VIN

AGND1

REF

CAP

AGND2

D15 (MSB)

D14

D13

D12

D11

D10

D9

D8

DGND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS8515

SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007

DB PACKAGE

(TOP VIEW)

Terminal Functions

TERMINAL

DIGITAL

DESCRIPTION

NAME

SSOP

I/O

NO.

AGND1

2

Analog ground. Used internally as ground reference point.

AGND2

5

Analog ground.

BUSY

26

O

At the start of a conversion, BUSY goes low and stays low until the conversion is

completed and the digital outputs have been updated.

BYTE

23

I

Selects 8 most significant bits (low) or 8 least significant bits (high).

CAP

4

Reference buffer capacitor. 2.2-

µF tantalum capacitor to ground.

CS

25

I

Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion.

DGND

14

Digital ground.

D15 (MSB)

6

O

Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or

when R/C is low.

D14

7

O

Data bit 14. Hi-Z state when CS is high, or when R/C is low.

D13

8

O

Data bit 13. Hi-Z state when CS is high, or when R/C is low.

D12

9

O

Data bit 12. Hi-Z state when CS is high, or when R/C is low.

D11

10

O

Data bit 11. Hi-Z state when CS is high, or when R/C is low.

D10

11

O

Data bit 10. Hi-Z state when CS is high, or when R/C is low.

D9

12

O

Data bit 9. Hi-Z state when CS is high, or when R/C is low.

D8

13

O

Data bit 8. Hi-Z state when CS is high, or when R/C is low.

D7

15

O

Data bit 7. Hi-Z state when CS is high, or when R/C is low.

D6

16

O

Data bit 6. Hi-Z state when CS is high, or when R/C is low.

D5

17

O

Data bit 5. Hi-Z state when CS is high, or when R/C is low.

D4

18

O

Data bit 4. Hi-Z state when CS is high, or when R/C is low.

D3

19

O

Data bit 3. Hi-Z state when CS is high, or when R/C is low.

D2

20

O

Data bit 2. Hi-Z state when CS is high, or when R/C is low.

D1

21

O

Data bit 1. Hi-Z state when CS is high, or when R/C is low.

Copyright © 2007, Texas Instruments Incorporated

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