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TMS320C6455BZTZ Datasheet(PDF) 29 Page - Texas Instruments |
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TMS320C6455BZTZ Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 250 page  TMS320C6455 Fixed-Point Digital Signal Processor SPRS276H – MAY 2005 – REVISED OCTOBER 2007 Table 2-3. Terminal Functions (continued) SIGNAL TYPE(1) IPD/IPU(2) DESCRIPTION NAME NO. EMIFA (64-BIT) - ADDRESS AEA19/BOOTMODE3 N25 EMIFA external address (word address) (O/Z) Controls initialization of the DSP modes at reset (I) via pullup/pulldown resistors AEA18/BOOTMODE2 L26 [For more detailed information, see Section 3, Device Configuration.] AEA17/BOOTMODE1 L25 Note: If a configuration pin must be routed out from the device and 3-stated O/Z IPD (not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied AEA16/BOOTMODE0 P26 upon; TI recommends the use of an external pullup/pulldown resistor. For more AEA15/AECLKIN_SEL P27 detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown AEA14/HPI_WIDTH R25 Resistors. AEA13/LENDIAN R27 O/Z IPU • Boot mode - device boot mode configurations (BOOTMODE[3:0]) [Note: AEA12/UTOPIA_EN R28 the peripheral must be enabled to use the particular boot mode.] AEA[19:16]: 0000 - No boot (default mode) 0001 - Host boot (HPI) 0010 -Reserved 0011 - Reserved 0100 - EMIFA 8-bit ROM boot 0101 - Master I2C boot 0110 - Slave I2C boot 0111 - Host boot (PCI) 1000 thru 1111 - Serial Rapid I/O boot configurations For more detailed information on the boot modes, see Section 2.4, Boot Sequence. CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode. • EMIFA input clock source select Clock mode select for EMIFA (AECLKIN_SEL) AEA15: 0 - AECLKIN (default mode) 1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK4 is selected as CPU/8 clock rate. • HPI peripheral bus width (HPI_WIDTH) select O/Z IPD [Applies only when HPI is enabled; PCI_EN pin = 0] AEA11 T25 AEA14: 0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 - HPI operates as an HPI32. • Device Endian mode (LENDIAN) AEA13: 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode(default) • UTOPIA Enable bit (UTOPIA_EN) AEA12: UTOPIA peripheral enable(functional) 0 - UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enable(default). This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins function as EMAC and MDIO. Which EMAC/MDIO configuration (interface) [MII, RMII, GMII or the standalone RGMII] is controlled by the MACSEL[1:0] bits. 1 - UTOPIA enabled; EMAC and MDIO disabled [except when the MACSEL[1:0] bits = 11 then, the EMAC/MDIO RGMII interface is still functional]. This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins now function as UTOPIA. And if MACSEL[1:0] = 11, the RGMII standalone pin functions can be used. Submit Documentation Feedback Device Overview 29 |
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