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IS63LV1024-10T Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc

Part # IS63LV1024-10T
Description  128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS63LV1024-10T Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE to Write End
7
7
8
ns
tAW
Address Setup Time to
8
8
8
ns
Write End
tHA
Address Hold from
0
0
0
ns
Write End
tSA
Address Setup Time
0
0
0
ns
tPWE
1
(1)
WE Pulse Width (OE High)
7
7
8
ns
tPWE
2
(2)
WE Pulse Width (OE Low)
8
10
12
ns
tSD
Data Setup to Write End
5
5
6
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE(2)
WE LOW to High-Z Output
4
5
6
ns
tLZWE(2)
WE HIGH to Low-Z Output
3
3
3
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN
DATAIN VALID
t LZWE
t SD
CE_WR1.eps


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