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SN74LVCHR16245A Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVCHR16245A Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQL OR ZQL PACKAGE (TOP VIEW) J H G F E D C B A 2 1 3 4 6 5 K GRD OR ZRD PACKAGE (TOP VIEW) J H G F E D C B A 2 1 3 4 6 5 SN74LVCHR16245A 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS582P – NOVEMBER 1996 – REVISED DECEMBER 2005 This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. All outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω series resistors to reduce overshoot and undershoot. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR. TERMINAL ASSIGNMENTS(1) (56-Ball GQL/ZQL Package) 1 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCC VCC 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCC VCC 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 xxxxx K 2DIR NC NC NC NC 2OE (1) NC – No internal connection TERMINAL ASSIGNMENTS(1) (54-Ball GRD/ZRD Package) 1 2 3 4 5 6 A 1B1 NC 1DIR 1OE NC 1A1 B 1B3 1B2 NC NC 1A2 1A3 C 1B5 1B4 VCC VCC 1A4 1A5 D 1B7 1B6 GND GND 1A6 1A7 E 2B1 1B8 GND GND 1A8 2A1 F 2B3 2B2 GND GND 2A2 2A3 G 2B5 2B4 VCC VCC 2A4 2A5 H 2B7 2B6 NC NC 2A6 2A7 J 2B8 NC 2DIR 2OE NC 2A8 (1) NC – No internal connection 2 |
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